The present invention relates to a semiconductor device including a serial reception circuit for oversampling a received serial signal with a plurality of multiphase clock signals having the same frequency but different phases to extract data and a data processing system, and to a technique effective when applied to e.g. a digital mobile phone system.
In electrical signals such as serial data of transmission signals and sampling clocks in reception circuits, time-base fluctuation in picoseconds or nanoseconds called jitter exists, and becomes a primary cause of transmission bit errors in high-speed transmission exceeding hundreds of megahertz. The causes of jitter include thermal noise of electrons and variation in propagation delay amount of an electronic circuit element due to power supply voltage or temperature variation. The jitter is classified into a plurality of parameters according to factor and fluctuation characteristics, and also treated differently according to measurement methods and technical fields. Random jitter is a jitter component of short-time nonperiodic fluctuation. The random jitter is strictly limited in a transmission standard, and taken into due consideration during circuit design. In addition, there exists another jitter component having periodicity associated with a clock frequency of an electrical circuit. Since such periodic jitter (in particular, a long-period component is also called wander) also impedes long-time continuation of stable transmission, a technique called CDR (Clock and Data Recovery) is required for the reception circuit of high-speed serial transmission.
The CDR is an electrical signal transmission technique for separating and extracting a data component and a clock component having an optimum phase relationship from an input serial signal, and is often used in a high-speed differential signal serial communication field. The CDR can be classified broadly into two methods.
The first method is a phase synchronization method using a PLL (Phase Locked Loop). In this method, the phase difference between a changing point of received serial data and a sampling clock edge is detected, and an incorporated VCO (Voltage Control Oscillator) is controlled by a charge pump, thereby reproducing a clock component synchronized with the serial data. The serial data is sampled based on the reproduced clock, thereby making it possible to reproduce a reception signal. In a narrow sense, the CDR often denotes the phase synchronization method. Japanese Patent Publication No. 4077454 describes a conventional technique using the PLL.
The second method is a phase interpolation method for oversampling received serial data with a plurality of multiphase clock signals having the same frequency but different phases. N multiphase clocks are generated from a reference clock, thereby obtaining N lines of sample data, using flip-flops. Then, a data signal having an optimum phase relationship with the clock is selected through digital signal processing, thus obtaining a reception signal. In general, the phase interpolation method facilitates the implementation and reduces the power consumption as compared to the phase synchronization method using the PLL. Japanese Unexamined Patent Publication No. 2002-190724, Japanese Unexamined Patent Publication No. 2005-192192, and Japanese Unexamined Patent Publication No. 2006-262165 describes conventional techniques using oversampling.